Re: Ultrawarp...

[mdj <mdj.mdj@gmail.com>]

On Thursday, 4 April 2013 08:45:24 UTC+10, Michael J. Mahon  wrote:

> If you think about what /RDY is expected to do, you can see why the
> 
> designer of an asynchronous cache-based accelerator would have trouble
> 
> justifying it on a cost/benefit basis. 

I might be reading it wrong, but it seemed to me that /RDY could be supported straightforwardly at 1Mhz. Doing it at 8Mhz seems like it would be hit and miss (pun intended) depending on the card in question, given that the relationship between a card using /RDY and the 6502 can be constructed deterministically and the introduction of an accelerator destroys any deterministic timing.

DMA on the Apple II works by stopping the clock input to the 6502, something a socket based accelerator could in principle detect, but as you say in a previous post the issue is cache-memory consistency, which will be inconsistent whenever /RDY or DMA is asserted. 

This can be solved, but only by being able to access the /INH line which is only available on the slots. Using /INH an accelerator can in principle substitute its cache for memory on appropriate accesses, allowing a DMA peripheral to see a consistent memory state. The same issues apply to /RDY.

As amusing as it is to consider a ZipChip with a couple of test-clip fly leads springing out of the potting, I for one am glad they didn't do that :-)