D Finnigan wrote:
Michael J. Mahon wrote:
A proper analysis would call for using a scope to check whether the
setup and hold times are being met by the card.
I would appreciated instruction on this procedure. I know how to use an
oscilloscope, but I don't know where I would place the leads in the
Apple,
nor what wave form I should look for.
The timing specs on the bus are pretty well documented in Sather's
book. Verifying that each signal the card sends to the bus is
stable for a sufficient amount of time prior to the next clock
(setup time) and that each signal is maintained for a sufficient
period of time after the clock (hold time) is painstaking to do
by direct measurement for each signal.
The usual culprits are late driver enables, relative to the bus
clock that samples the data lines, or enables that end too soon.
Of course, the card must also read addresses and data sent to it,
so whatever on-card clocks are used to latch these signals must
be within the timing window for the latching device.
It would be best to start with a static timing analysis working
from a schematic of the card and the specs of the chips. This
will identify signals that have tight margins. The signals and
associated latching clocks can then be probed to verify timing
constraints are (or are not) satisfied.
If there are multiple logic levels on the card, then there may
be internal clocking involved, as well, though most Apple cards
are not that complex.