Re: Pot on Language card: what for?

[dempson@actrix.gen.nz (David Empson)]

Michael J. Mahon <mjmahon@aol.com> wrote:

> Linards Ticmanis asked:
> 
> >another stupid question. I have two II+ language cards, the standalone
> >versions that do their own refresh and that don't need a cable to one of
> >the RAM chips on the II+ motherboard.
> >
> >Those cards have one pot each on the PCB. What does this pot do? Adjust
> >refresh cycle time maybe? Which way would you have to turn it for slower
> >refresh, if that is the case?
> 
> I would hope not!  The least I would expect of on-card generated refresh
> is that it is synchronous with the Apple bus, so it could refresh in the
> video access time slot, and always appear ready to the processor.

The card could be using the bus clock to synchronize the refresh cycles
so that they occur during the "video" portion of the CPU cycle, but
still using an on-card timer to control the refresh rate.

A "normal" DRAM refresh selects an entire row, which refreshes several
locations at the same time.  The refresh circuit needs to count through
all of the available columns and get back to the first column in time to
satisfy the refresh timeout of the DRAM.  (Or is it the other way
around?  No matter, the explanation works either way.)

This is typically in the order of 2 milliseconds, so with 128 columns
and 128 rows (16Kbit), a refresh access cycle is required about once
every 16 microseconds.

Using an RC circuit to implement a delay for this might have saved
adding another chip to the card.

The Apple II's innovative use of the video access cycles means that it
can get away without any explicit refresh cycles.  The video accesses
are considerably faster than the requirements for refreshing DRAM.


Having said all that, I'm starting to doubt it myself.  It would be
easier to use Phi0 or Phi1 as a clock for the refresh counter.

Some other possible explanations for the pot:

- A voltage adjustment for fine tuning a power supply input to RAM chips
(older DRAM typically requires at least two supply voltages, +5V and
-12V if I remember right).

- A delay adjustment to precisely control access cycle timing (e.g. to
ensure that the data bus driver is enabled after the DRAM is outputting
valid data).

- A delay adjustment or power supply threshold to ensure that the card
operates predictably at startup (seems less likely - RESET would serve
for this).