Re: ZipGS cache behaviour (was Re: ZipGSx Upgrade Questions)

[salfter@salfter.ncc74656.dyndns.org (Scott Alfter)]

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In article <1ek24v9.1fc7s2n67vhmmN%dempson@actrix.gen.nz>,
David Empson <dempson@actrix.gen.nz> wrote:
>The following program does the trick.  It runs at $0300 under
>BASIC.SYSTEM (or even if you Ctrl-Reset from the "Check startup device"
>screen).

Neat program...somewhat like the CACHECHK program that came out a few years
ago to weed out cheap motherboards (mainly 486 boards at the time) with fake
L2 cache.

>Now for some real tests: my system is a ROM 3 IIgs with 4 MB memory card
>(5 MB total) and an 8 MHz ZipGS with 16K of cache.

Mine's a ROM 01 with an extra 4 megs (total 4.25 megs) and a 12.5-MHz ZipGS
with 64K cache.  (It started out like yours, but I upgraded it a while
back.)

>At normal speed: all banks take 48 ($30) cycles.

That's what I observed.

>At fast speed, Zip disabled: all banks take 20 ($14) cycles.

Ditto.

>Zip enabled (8 MHz): banks $00 to $2F take 8 cycles, banks $30 to $4F
>take 14 or 15 ($0E or $0F) cycles.

On mine, all banks took 6 cycles.

Time to get a table going:

configuration      1 MHz 2.8 MHz max speed notes
================== ===== ======= ========= ======================
stock IIGS           48     20      20
with ZipGS 8/16      48     20     8/14    not cached beyond 3 MB
with ZipGS 12.5/64   48     20      6

>I like it when my theories turn out to be more or less right.  :-)

With x86 hardware, the cacheable area of a particular processor or chipset
is something to take into consideration.  The Intel 430VX and 430TX chipsets
are considered fairly lame as far as Socket 7 chipsets go because they can
only cache up to 64 megs, for instance.  With some chipsets (the VIA MVP3
comes to mind), the cacheable area is determined by the amount of cache. 
Who would've thought the same considerations apply to accelerated Apple IIs?
:-)

  _/_
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(IIGS(  Scott Alfter (remove Voyager's hull number for email address)
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