Re: ZipGS cache behaviour (was Re: ZipGSx Upgrade Questions)

[apple2pd@garp3.icaen.uiowa.edu (ground.ecn AppleII Librarian)]

In article <1ek24v9.1fc7s2n67vhmmN%dempson@actrix.gen.nz>,
David Empson <dempson@actrix.gen.nz> wrote:
>
>The end result will be a table at memory locations $1000 to $107F which
>contains the number of 1 MHz cycles required to do the ten CMP
>instructions (plus a little overhead) for each bank, or $00 if that bank
>doesn't exist.  These should be roughly the same for each bank, except
>where a cache/noncache boundary is crossed, at which point it will show
>significantly larger values.
>
>If the IIgs was running at normal speed (1.023 MHz), I'd expect 48
>cycles to elapse between the two references to the horizontal counter.
>
>Now for some real tests: my system is a ROM 3 IIgs with 4 MB memory card
>(5 MB total) and an 8 MHz ZipGS with 16K of cache.
>
>At normal speed: all banks take 48 ($30) cycles.
>
>At fast speed, Zip disabled: all banks take 20 ($14) cycles.
>
>Zip enabled (8 MHz): banks $00 to $2F take 8 cycles, banks $30 to $4F
>take 14 or 15 ($0E or $0F) cycles.
>

David, thanks for cachetest pgm.  I ran it on my Rom 1, ZipGS 8/64.
Here is my result:

Zip enabled (8Mhz, 64k cache): banks $00 to $41 take 8 cycles, banks $42
and higher through $7f are $00 .

I'll try it at home on my Rom03, also with a ZipGS 8/64.

  --Steve

-- 

 --Steve  (apple2pd@ground.ecn.uiowa.edu)