Re: Super GS

[Bill Heineman <burger@contrabandent.com>]

> 
> Yes, it would. The manufacturing technology required probably limits that
> sort of approach to someone like Apple.
> 

Not anymore. You see the CPU port of the IIgs goes at a speedy (Sarcasm) 2.6
Mhz. This is considered snail speed by most modern gate arrays. So
therefore, you look in the catalog for the cheapest part and it will still
outrun the bus by a large factor. Most parts I look at are in the 50mhz
range to start.

Next, ANY add-on CPU will be an engineering problem. The ZipGS was a prime
example. They had two engineers working full time for almost 2 years to
perfect the gate array, and they already had a model (The ZipIIe) to start
with. The problem was that they were designing what we call today an L2
cache to run on top of a 65816 to accelerate it. Adding an L2 cache to a
chip that was never designed to have one and then make it work with a
machine that never had one was an engineering marvel.

Now, fast forward to today. All major CPU's contain L1 (Even better) and L2
caches right in the chip. All you need to do is tell in software what areas
of the computer you don't want this feature enabled. So the hardware to
graft a StrongARM or PowerPC into a IIgs is trivial compared to making a
ZipGS. The only real challenge is writing the 65816 emulator to match cycle
times to allow things like the disk drive to operate.

Burger