Re: Carte Blanche Atto (CB for the IIc)

["Charlie" <charlieDOTd@verEYEzon.net>]

"Steven Hirsch" <snhirsch@gmail.com> wrote in message 
Yq2dnT-HBr7z5w3QnZ2dnUVZ_h2dnZ2d@giganews.com">news:Yq2dnT-HBr7z5w3QnZ2dnUVZ_h2dnZ2d@giganews.com...
> On 03/27/2011 10:12 AM, Steve wrote:
>> Hi All,
>>
>> I havent had the chance to drop in much, but I have been busy
>> tinkering with II stuff in my spare time. Although its been at a
>> snails pace, I have managed to prepare a prototype of Carte Blanche
>> intended for the IIc (called CB Atto). Its a pretty tight fit and
>> seems to just clear at the moment. There's still a long way to go with
>> programming etc, but so far it feels like a good start and has passed
>> all of its tests. I hope to see if Alex has the time to port JAT over
>> to it at some point. Either way, its been an interesting experimental
>> board.
>
> Steve,
>
> As always, you do great work!
>
> However, (and please take this as constructive criticism) it would be very 
> helpful if some of that creative energy went into system documentation for 
> the original CB.  In particular, it's very difficult for a beginner in the 
> field of HDL and FPGAs to get a foothold on the device.  I'm sure all the 
> details are there, but I would love to see some more high-level discussion 
> of the CB architecture.

I too would like see more discussion.  Sometimes I feel like I'm the only 
one doing anything with the CB and much of the time I'm lost.  Still I have 
learned a little bit so maybe I can help.

> For example:
 > - How does it map to the host bus and what would a basic interface scheme
> "look" like in terms of mapping logic to the symbolic port connections?

As Glenn mentioned, you start with the schematic (CBSCH01.pdf).  Page 5 has 
the Apple II slot
definition.  If you follow any wire from the slot connector (yellow) to the 
column on the right (blue) you will see the name for that wire in the 
Carteblanche1 module.  And as Glenn, Rich and Bill pointed out the names 
used are defined in the UCF (user constraints file).
In the beginning of any module you write you enter the inputs and outputs by 
the names defined. For instance in the cb1.v (Carteblanche main module) file 
you have the "input BUS_3M58".
Looking at the UCF you'll see 'NET "BUS_3M58" LOC = P51;', meaning BUS_3M58 
is connected to pin 51 on the FPGA.  Again looking at the schematic you'll 
see that BUS_3M58 is connected to pin 35 on the Apple II slot connector so 
pin 35 on the Apple is connected to pin 51 on the FPGA. Much of the work has 
already been done for you with the cb.ucf at least for the Apple II slot, 
the RGB output, the SD, etc.

As far as mapping logic to the symbolic port connections here is trivial 
Verilog example of what I think you mean:

/*---------------------------------------------*/
module test (input BUS_3M58, input BUS_PHASE0, input SYSCLK, output 
IDE_ACT);
                      // SYSCLK is the onboard 14.31818MHZ oscillator
reg do_something;     // create a register to hold our logic

always@(posedge SYSCLK) // everytime the clock goes high
 begin
 do_something <= BUS_3M58 & BUS_PHASE0;  // 'and' the 2 inputs & store 
result
 end

assign IDE_ACT = do_something;  // output result to pin 16 of IDE connector
endmodule
/*--------------------------------------------*/

Disclaimer:  I haven't tried this.  It's just to give you some idea of how 
it works.

> - Maybe a raw beginner's project that does something simple like embed 
> 6502 code in a ROM area on the FPGA and permit it to be switched in and 
> executed from the host.

I've been thinking about doing something like this myself.  I believe Alex 
does this for the floppy disk and z80 code, so there should be some ideas 
there.
Incidentally, its very easy with the existing CB code to add the ability to 
*see* any peeks/pokes to any location in the IO area.  This makes it nice to 
play around with your logic by pokeing values into unused IO locations.

> - How does the ASIC adapter map to the FPGA?  What would a "framework" 
> that ties in a device on a that board look like and how are the pin 
> connections referenced symbolically?

I'm assuming the ASIC adapter is what is referred to in the schematics (page 
7) as the Peripheral BD Interface.  If so I believe you would use the UCF 
file to define the pins and symbols in the same way as the Slot connector is 
done.

> A lot of that information is probably implicit in Alex's designs, the 
> schematics and the Xilinx databooks, but for the uninitiated the initial 
> learning curve is quite steep.

I agree, I have been muddling around with this myself, but you just have to 
start with something and learn a little bit at a time.

> I've been sitting here with two boards for over a year and have not been 
> able to negotiate it.

I started by studying Alex's code and tentatively trying to change things. 
Most everything fails but occasionally I succeed and that feels good.

> I do have a reasonable amount of background in logic design, but it dates 
> strictly from the TTL 74LS* era.  There are just too many pieces that need 
> to get sewn together at present for me to get a foothold, and I suspect 
> it's been daunting for some others of us as well.

You're way ahead of me there.  I have very little knowledge of logic design, 
so I've had to try to learn that along with learning Verilog, FPGA's in 
general, the Carteblanche in particular and Xilinx's overwhelming tools.  I 
also have found out that I know less about the hardware end of the Apple IIs 
than I thought I did.

Anyway, if I can help you get started just ask.  Either email me or better 
yet ask here because I'm sure others will join in.

Charlie