Re: Carte Blanche Atto (CB for the IIc)

[a2retro <a2retrosystems@gmail.com>]

On Mar 28, 8:09 am, Steven Hirsch <snhir...@gmail.com> wrote:
> On 03/27/2011 10:12 AM, Steve wrote:
>
> > Hi All,
>
> > I havent had the chance to drop in much, but I have been busy
> > tinkering with II stuff in my spare time. Although its been at a
> > snails pace, I have managed to prepare a prototype of Carte Blanche
> > intended for the IIc (called CB Atto). Its a pretty tight fit and
> > seems to just clear at the moment. There's still a long way to go with
> > programming etc, but so far it feels like a good start and has passed
> > all of its tests. I hope to see if Alex has the time to port JAT over
> > to it at some point. Either way, its been an interesting experimental
> > board.
>
> Steve,
>
> As always, you do great work!
>
> However, (and please take this as constructive criticism) it would be very
> helpful if some of that creative energy went into system documentation for the
> original CB.  In particular, it's very difficult for a beginner in the field
> of HDL and FPGAs to get a foothold on the device.  I'm sure all the details
> are there, but I would love to see some more high-level discussion of the CB
> architecture.
> For example:
>
> - How does it map to the host bus and what would a basic interface scheme
> "look" like in terms of mapping logic to the symbolic port connections?
>
> - Maybe a raw beginner's project that does something simple like embed 6502
> code in a ROM area on the FPGA and permit it to be switched in and executed
> from the host.
>
> - How does the ASIC adapter map to the FPGA?  What would a "framework" that
> ties in a device on a that board look like and how are the pin connections
> referenced symbolically?
>
> A lot of that information is probably implicit in Alex's designs, the
> schematics and the Xilinx databooks, but for the uninitiated the initial
> learning curve is quite steep.  I've been sitting here with two boards for
> over a year and have not been able to negotiate it.  I do have a reasonable
> amount of background in logic design, but it dates strictly from the TTL 74LS*
> era.  There are just too many pieces that need to get sewn together at present
> for me to get a foothold, and I suspect it's been daunting for some others of
> us as well.
>
> Anyway, sorry to sound critical.  Maybe it's just me that's dense :-).
>
> Steve

Hi Steve,

I understand where you're coming from but maybe I am a little bit more
comfortable with things as I have dabbled with the xilinx tools for a
few CPLD projects. Logic design aside, the FPGA mounted on the
CarteBlanche is same as any other CPLD/FPGA trainer out there.

It' simply a FPGA that has it's i/o's prewired to various hardware
ports on the card. To understand how that relates to anything, you
really need to study the schematic. Start by finding the page with
host bus signals, follow them through the level translator chip to the
particular pin on the FPGA. In order to use that information you need
to make a UCF file (pin to signal map file) or ask someone who has
already made one to give you a copy. There will be some signals in
there that are constant (a2bus signals for example) and others that
will be project dependent.

Once you understand that much, then you can start to think about how
you might use those i/o's and the internal logic building blocks in a
simple project.

I think your suggestion of emulating the onboard ROM of a peripheral
card is a useful example and one that I want to know how to get
working. I can think of a simpler first step and that is emulating
registers for any peripheral card. So basically, be able to read data
from the a2 bus, store it in a buffer and write it back when
requested. Once you have that you can add ROM emulation. Take those
two pieces and generate addressing/chip enablement to the on board
SRAM and you have a 512K ram card.

If your game I'd be willing to work with you something like that (I've
done it with a CPLD using ABEL).

Glenn