Re: Wozniak vs Jobs

[jerryp@__Mmmmunch__.ziprobes.com (Jerry Penner)]

In article <1998042816321400.MAA29168@ladder01.news.aol.com>, regnirps@aol.com (Regnirps) wrote:
>I think you are confusing MHz with MIPS. A 65C02 typical instruction is four
>cycles and an ARM instruction is one cycle. So, simpy on a cycle count you get
>about a 24 to 1 advantage for the 6MHz ARM. When you add the 32 bit width and
>look at typical operations like additions of 16 or 32 bit niumbers or address
>calculations, you get another factor of 4 or more. In other words, about a 100
>to 1 performance ratio for a 6MHz ARM and a 1 MHz 65C02. Emulation of a 1 MHz
>65C02 is trivial.

Well, has it actually been done?  Or is this just hypothetical?

For one thing, lots of 65c02 instructions execute in 2 clock cycles.  When 
you're building an emulator, you've got to do a few other things besides 
just map opcodes from one CPU to another.  When emulating an 8-bit CPU's 
arithmetic, it doesn't matter all that much if you can do 32-bit 
calculations, you still have to emulate the 8-bit ones 8-bits at a time.  
Basically, I think it is realistic to suggest that the 6 MHz ARM could run 
2-4 times as fast as the 6502 at the same clock speed, giving a 12-24 times 
speed increase at 6x the clock speed.  If your CPU emulator can guarantee 
you have only 12-24 instructions to execute in order to emulate one 6502 
instruction, great!  It also depends on how memory and I/O is emulated.  
These things are usually fairly expensive.  I suppose Apple could have 
developed some hardware that would help this out.  On a pure software 
emulator, I think you must be dreaming.

>>Sure, but will he verify all these great claims you keep making
>>about the ARM itself?
> 
>Sure, consider them verified.

Ok, can you tell us some more about the hardware and software in this 
thing?  I for one am curious to know how this thing ticked?


--
Jerry Penner		Jerry_Penner at ZIProbes dot Com