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Re: IIgs Zip accelerator SRAM speeds
- Subject: Re: IIgs Zip accelerator SRAM speeds
- From: sbehrens@bigfoot.com (Sönke Behrens)
- Date: 1997/08/28
- Newsgroups: comp.sys.apple2
- Organization: Nerd's Revolutionary Front
- References: <5tsopj$gt5@gandalf.Advent.COM> <19970827230343817275@dempson.actrix.gen.nz>
Devin,
>Now for the explanation of why you need faster TAG RAM at higher speeds:
>there are probably delays introduced by discrete logic and/or the ASIC
>itself, which use up a constant amount of time. At lower frequencies
>this isn't significant, but as the clock frequency increases you need
>substantially faster TAG RAM to compensate for this fixed delay.
Do you also have a theory on the reports that it helps stability to
_slow_ the data ram down a bit? I.e. use 30-45ns DATA RAM instead of
12-15 ns for both TAG and DATA.
Soenke
--=20
ORCA/C buglist and other stuff at: http://www.arrowweb.com/sbehrens/