Re: Zip GS questions

[Mark Wade <mwade@suffolk.lib.ny.us>]

On 16 Dec 1996, Mitchell Spector wrote:
>     If your board is filled with 32K x 8 SRAMs (64K of cache) then
> how is it possible to configure it to recognize only 8K or 16K of
> cache memory? From my own experience, by flipping the DIP switches,
> I can tell my card to "see" both 32K banks (64K) or only one of them
> (32K). If I set the DIP switches for 8K or 16K, the ZipGS _instantly_
> starts crashing and will be totally unusable. That is, it can't even
> get as far as launching the Finder desktop because it then thinks
> there are lower-density chips installed.
>
>     I would think if you want to toggle between 8K and 16K, you would
> need 8K SRAMs in all four sockets.
>
>     In otherwords, if you have 8K or 32K of cache on your board (only
> two sockets filled) there is no way to toggle the size. If you have a
> board with 16K or 64K (four sockets filled) you _can_ toggle your cache
> size, but only cut it by half by telling the board to ignore the second
> set of chips. In my case I can toggle between 15/64 and 15/32, and on
> my previous board I could toggle between 8/16 and 8/8. This is correct,
> isn't it? (If not, someone please correct my assumption :)
>
> Mitchell Spector
> spec@vax2.concordia.ca


Hmmm... That's all interesting and sounds quite logical, especially
the part about needing lower density chips to set the switches to
8 or 16 k.  I can't explain it but I have my ZipGSX running at
12mhz, 64k cache and am able to set the switches to 8, 16, 32, and
64k and that is what is reported by the Zip CDA.



Mark Wade
mwade@suffolk.lib.ny.us
m.wade7@genie.com
mswade@delphi.com