Re: New IIgs Accelerator.... Wow!

[Eric Rucker <bhtooefr@gmail.com>]

On Jun 13, 10:07 pm, Michael J. Mahon <mjma...@aol.com> wrote:
> It is quite likely that any "speed option" would not vary the clock
> speed, but would only insert additional delays, so power effects would
> be minimal.
>
> I doubt that any technology that permitted compact chip-like packaging
> would dissipate enough power to present any problems.

The power necessary to burn traces is in the multiple amps range, at
the voltages involved in an Apple II.

I'm assuming this is implemented using an FPGA and a couple SRAMs.
Those aren't *capable* of drawing enough current to even think of
lifting the traces.

As far as high clock speeds... I'm an electronics newbie, but the
worst I can think of is noise, either from other things in the IIGS,
or from the accelerator itself, and even then, enough decoupling, and
good enough circuit design on the accelerator itself, and I don't
think that'd be much of a problem - most likely less of a problem than
it is on a TransWarp GS or Zip GSX, in fact.