Re: ZipGS stability at 15 MHz - update

[wbaguhn@nyx10.cs.du.edu (Will Baguhn)]

In article <9JUL199605090893@vax2.concordia.ca>,
Mitchell Spector <spec@vax2.concordia.ca> wrote:
>In article wbaguhn@nyx10.cs.du.edu (Will Baguhn) writes...
>>
>>Hmm... what are the speeds of those SRAMs?  You didn't happen to damage
>>the trace at J8, did you? (perhaps for a split-16k cache?)
>
>   The ZipGS sockets have been set-up to accept both wide and narrow SRAMs
>(in my board narrow chips are installed in TAG, wide ones in DATA). TAG
>is using 15ns rated chips (Goldstar?), DATA is using 45ns (Sony). 
>
>>The faster SRAMs should always go in the TAG sockets.  It may be that you
>>have a toasted upper-half of the cache.  if so, only one may be toasted...
>>process of eliminiation should show you which chip.
>
>   I should note one other thing. Although this board is running at
>15 MHz, it has an older ASIC with _no_ rewiring or modifications to
>it. The production date code on the 'ZipChip' ASIC is Febuary 1991.
>Perhaps this is also the reason all detection utilities rate my
>speed as 14.93 MHz even though a 60 MHz oscillator is installed.
>
>   I'm running more or less stable now with the board set as a 15/32,
>so that doesn't seem likely. Why isn't the new ASIC mentioned in the
>upgrade FAQ btw, or do the newer 65C816-14's (non-E) make this moot?
>
>Mitchell Spector
>spec@vax2.concordia.ca

Is 45ns really fast enough to keep up with 15 MHz?  That's my guess..
and it is a shot in the dark, but it's a half-decent shot in the dark.

Does it work with the 64k cache if you slow it down to 7 MHz again?  If
that's the case, I'd be a lot more sure that speeding up your DATA SRAMs
would make things happier.
-- 
                                      --- SPQR (wbaguhn@nyx.net)