Re: CACHE????

[rubywand@aol.com (RUBYWAND)]

In article <31D9D33E.4144@cup.hp.com>, Michael Mahon <mahon@cup.hp.com>
writes:

>....
>It isn't ROM code--it's hardware!  This is in a PLA (or two--I don't
>have one myself) and the cache addressing must be done on *every*
>cycle of the faster clock.  ROM code is out of the question.
>....
>

     Yes; my mistake was in assuming that Zip-GS would have a nice,
separate ROM which would contain 65C816 cache setup instructions. For
example, the '816 would check dip switches and initialize latches to match
size of on-board cache. Naturally, the actual cache address decoding would
have to be handled by fast logic.

     As Neil pointed out, 'there ain't no ROM'-- at least, if there is, it
is inside the ZipChip. If there is cache setup code executed by the '816
and if the ZipChip can handle more than 64K cache (perhaps with a minor
hardware add-on),  then an extension PROM should allow expanding cache
size.

     Since so much of Zip-GS is in the ZipChip, it would help to know
specifics of the IC's layout and operation. Some of this info is certain
to be proprietary-- like PAL 'programming'. Still, if the IC is some kind
of standard vendor-programmable micro-controller, then quite a few details
may be available in some data book. The markings on my 10/64 Zip-GS's
ZipChip are ...

ZIP SFMAJVZGS
Zip Chip
7340-18B
9109 W4886
.   

Rubywand