Re: WDC Chip Order Update

[cdeschu@nyx10.cs.du.edu (Chris Deschu)]

In article <39ku92$o1f@news.service.uci.edu>,
Trangdaithi Hoang <thoang@orion.oac.uci.edu> wrote:
>In article <39kqhj$oif@blackice.winternet.com>,
>Frank M. Lin <fmlin@icicle.winternet.com> wrote:
>
>>2. My new 14 MHz does not work properly even at 12.5 MHz.  It crashes
>>more often than the engineering sample (paid $100 for it about 2
>>years ago) I have.  One other friend's does not even work at all.  
>>
>>There are couple of success stories, of course.  Give me some time, and
>>I will try to get more data/info...
>
>I don't have any hard data, but my hunch is that the new 14 MHz WDC
>65c816 is manufactured using .8 micron process which means less
>output drive capability on the I/O lines (data, address, etc) than
>the Engineering part manufactured using probably 1 micron process.
>This could explain why the Engineering part appears to work better
>than the new 14 MHz part on an unmodified accelerator.  Buffering
>the I/O lines should help.

Hmm, this is interesting. My Engineering part won't go over 10mhz
reliably, and I have fast ram and gals. I have avoided buying one
of the new 14mhz chips because of nightmare stories like this.
Could you please tell the unenlightened of us *exactly* how to go
about "buffering" the I/O lines? I did take some electronics
courses, but I'm not familiar with what you are saying. In case you
have not guessed, I have a TransWarp GS, but I'm sure the information
would be useful to those with ZipGS' too. Thanks!

-- 
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 |___              Chris Deschu                       cdeschu@nyx.cs.du.edu
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