Re: wanted:info on IIe extension

[dempson@actrix.gen.nz (David Empson)]

In article <35leuq$9p2@gap.cco.caltech.edu>,
Nathan Mates <nathan@cco.caltech.edu> wrote:
>
> TRB and TSB are useful for and/or'ing the accumulator against a
> value, leaving the result in the accum and the value (and some flag
> fun)... [For example, stz 00 / lda #$7F / TSB 00 leaves 7F in A and
> 00.]

I thought I'd better correct and clarify that.  The accumulator is NOT
affected by a TRB or TSB instruction.

As indicated in Nathan's list of opcodes, TSB and TRB stand for "test
and set bits" and "test and reset bits".  They are similar to a
combination of the BIT instruction with an OR or AND operation.

TSB location

1. Bit-test the accumulator against the memory location and leave the
result in the Z flag.  Similar to BIT location, but doesn't affect N/V.
2. OR the accumulator and the memory location, leaving the result in
the memory location.  The accumulator is unchanged.

(i.e. set bits in the memory location after testing them)

TRB location

1. Bit-test the accumulator against the memory location and leave the
result in the Z flag.  Similar to BIT location, but doesn't affect N/V.
2. AND the complement of the accumulator with the memory location,
leaving the result in the memory location.  The accumulator is unchanged.

(i.e. reset bits in the memory location after testing them)

e.g. LDA #$20, TSB loc  will set bit 5 in "loc" and set Z if the bit was
                        previously clear.
     LDA #$20, TRB loc  will clear bit 5 in "loc" and set Z if the bit was
                        previously clear.

These instructions are useful for implementing semaphores - you can
set a bit and test if it was previously set, without any possibility
of being interrupted between the two operations.  (This can also be
done with other instructions such as INC, but TSB/TRB are cleaner.)


A few other "new features" and caveats in the 65C02:

1. Undefined opcodes are now "NOPs".  On the 6502, undefined opcodes do
weird things (they have been documented somewhere).  Note that opcodes
which are not defined on the 65C02 _are_ defined on the 65802 and
65816, which uses all 256 opcodes (except $42, WDM, which is reserved
as a prefix byte for future 65xxx family micros).

Some copy protected programs rely on the behaviour of undefined 6502
opcodes.  e.g. the original version of Apple LOGO uses an undefined
opcode in its boot code, preventing it from booting on a 65C02 or
later CPU.

2. JMP indirect in the 6502 has a bug: if the indirect pointer is on a
page boundary, i.e. JMP ($xxFF), then the 6502 doesn't increment the
high order byte of the address to fetch the high order byte of the
jump destination.  The 65C02 fixes this.

e.g. if you use JMP ($20FF), the 6502 will fetch the jump address from
$20FF (low byte) and $2000 (high byte).  The 65C02 will fetch the high
byte from $2100.

3. Decimal mode implements the N, V and Z flags, at the expense of one
additional clock cycle for each ADC/SBC in decimal mode.

There are a few minor changes to do with read/write cycle details,
BRK/interrupt interaction, and the state of the decimal mode flag after
a reset or interrupt.


If you're used to using the BIT instruction to test memory locations 6
and 7, note that this does not apply to the BIT IMMEDIATE instruction.
It only affects the Z flag.


One final point: the enhanced IIe's disassembler and mini-assembler do
not support the new 65C02 instructions.  (They are supported on the
IIc, IIc+ and IIgs.)  You will have to enter opcodes directly in the
monitor, and do a little hand-disassembly when using the L command.
-- 
David Empson
dempson@actrix.gen.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand