Re: Flame-o-Rama! (was Re: ZipGS 12MHz on

[philip@labtam.oz.au (Philip Stephens)]

Jim Wong writes:
>What are you talking about?  I was not aware that the 65816 has an instruction
>pipeline of any considerable length.

  The 65816's pipelining is sufficient to ensure that almost all cycles consumed
by an instruction are memory cycles.  For example, take the ADC immediate
instruction: in 8-bit mode, it only consumes 2 cycles, which are the cycles
required to fetch the instruction!  The instruction decoding takes place
while the operand is being fetched, and the addition takes place while the
opcode of the next instruction is fetched.  All other instructions have
similiar pipelining.
  The 65816 doesn't have the RISC type of pipelining where the instructions
pass through an internal queue to maximise parallel execution of instructions
and hence reduce the effective instruction time to a single cycle.  But most
CISC processor's don't even do as much as the 65816 does to reduce instruction
execution time.

>For what it's worth, though, a 40 MHz 68040 would probably eat a 12 MHz 65816
>for lunch.

  Now that I think of it, 40 Mhz was being a little optimistic.  But to get
back to the matter at hand, the 680x0 series requires several clock cycles
just to fetch a value from memory i.e. it doesn't to my knowledge use any
pipelining at all.  Hence it effectively runs four times slower at the same
Mhz rating.  I'm not sure on the exact data for the 80x86 series, but it's
probably similiar.




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