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Re: Fastest TWGS and ZIP GS
- Subject: Re: Fastest TWGS and ZIP GS
- From: foegelle@sleepy.cc.utexas.edu (Michael Foegelle)
- Date: 8 Oct 1993 12:12:05 -0500
- Newsgroups: comp.sys.apple2
- Organization: The University of Texas - Austin
- References: <28v7in$eav@sleepy.cc.utexas.edu> <29434c$ltf@r-node.io.org>
In article <29434c$ltf@r-node.io.org>, Brian Tao <taob@io.org> wrote:
>In article <28v7in$eav@sleepy.cc.utexas.edu>, Michael Foegelle writes...
>>
>> Well, damn, this did become a long winded discussion anyway, but maybe
>> that'll help people understand why the change in supply voltage allows
>> the CPU to be pushed to higher frequencies.
>
> That was great! I'm filing this one away for sure. ;-) So by
>pumping up the voltage, the signal rises much faster and thus reaches
>the threshold in less time?
Thanks, glad you liked it. As for the last question, it kind of depends on
your viewpoint. Basically the signal rises to Vsource at the same rate,
but if Vsource is increased while Vlogic-high remains the same, it reaches
Vlogic-high faster. Of course there are other complications involved with
all of this, but inductance causes the most of the trouble. The point still
remains that the signal has to reach and remain in a certain state long
enough for it to register at the load... Increasing the source voltage can
only help so much. Eventually you'd overload the chip(s) and burn 'em up!
>--
>Brian Tao:: taob@io.org (Internex Online, 416-363-3783, 17 lines, v.32bis)
>::::::::::: 90taobri@wave.scar.utoronto.ca (University of Toronto, 9T4)
>
Michael Foegelle
--
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