Re: ZipGS Tech. Question

[dempson@swell.actrix.gen.nz (David Empson)]

In article <259do2$3f9@reeve.research.aa.wl.com> schultp@aa.wl.com (Paul Schultz) writes:
> Could someone explain the DATA and TAG cache memory designations
> on the ZipGS card? Why did my card come with one (TAG or DATA, I 
> can't remember which right now) with slower SRAM chips than the
> other? I believe the TAG had 70ns chips and the DATA had 45ns
> chips when I got it.

The general principle is that the Tag RAM contains information about
which parts of the Data RAM contain valid memory values, and where in
memory they come from.

I don't know the exact method the ZIP uses here, but it is probably
something like this:

A TAG byte contains the bank number for the corresponding DATA byte.
If the location is invalid, the TAG byte will contain a special value
(which is an illegal bank number, e.g. $80).

The corresponding DATA byte contains the contents of that memory
location (as last read or written).

If I'm right, then this means the ZIP cannot simultanously cache a
byte at the same offset in two different banks.

On second thoughts, there must be more to it than this, because there
isn't enough resolution to support an 8k cache.

Perhaps there are two tag bytes and two associated data bytes.  In
this case, the tag bytes will be divided into an address field and two
flag bits indicating which of the two data bytes are present in the
corresponding cache location.

The 24-bit memory address would be subdivided as follows:

Bit 0: used to select the appropriate "present" flag in the Tag RAM.
Bits 1-14: mapped directly to the address bus of the Tag and Data RAM.
Bits 15-23: stored into the Tag RAM.

This would mean that there is only one cache location that can be used
for a byte at a particular offset from a 16k memory block.  For
example, memory locations $02/0000, $02/4000, $02/8000, $02/C000,
$03/0000 etc. would be stored at the same location in the Data RAM, so
they couldn't be cached simultaneously.  Since the Data RAM addresses
work in pairs, you could cache $02/0000 and $02/0001 at the same time,
but couldn't cache $02/0000 and $02/4001 simultaneously.

With 16k of cache RAM, the ZIP probably either provides two alternate
locations for the same memory address, or doubles the "chunk" size to
32k (more likely).

With 32k of cache RAM, the ZIP could use a 64k chunk size, and a 64k
cache would allow a 128k chunk size.


I don't know why the Tag RAM might be slower.  Going by my theory, it
seems more likely that the Data RAM would be the slow one.

The ZIP probably reads the TAG and DATA simultaneously, then decides
whether to keep the data value or read it from the IIgs, based on
whether the TAG value matches the bank being read from.

If I'm right about the paired locations, then it would need to read
the Tag RAM twice for each memory access.  It can probably eliminate
the second read by looking at the "valid byte" flags and partial
address stored in the first tag byte, then only needs to read the
second tag byte if there is a potential match.

All IMHO, and much theorising going on, of course...
-- 
David Empson                                                               
dempson@swell.actrix.gen.nz                                                
Snail mail: P.O. Box 27-103, Wellington, New Zealand