Alex Freed wrote:
mdj wrote:I did notice this issue though during initial testing last weekend and figured it could be worked around by placing an open-collector inverter against whatever output is driving the ready state LED: simply have the inverters open collector output hold reset low until the FPGA signals it's ready on that line, and when the inverter changes state /RESET will again be pulled high by the Apple II.Maybe even better - there is an internal signal telling that not only is the configuration finished but the clock DLL is also locked. Can be routed to some FPGA pin and used to drive that inverter. Pins are tri-state before the configuration is done.Having said that IMHO having to do a CTRL-reset just once after a power-up is not such a big deal.
Isn't that usually a re-boot on an auto-boot machine? If I reset my //e, my Zip Chip accelerator is reset, requiring a re-boot to re-establish it's slot/device acceleration configuration. Seems better to have a clean start. -michael NadaNet 3.0 for Apple II parallel computing! Home page: http://home.comcast.net/~mjmahon/ "The wastebasket is our most important design tool--and it's seriously underused."