Re: DMA at 2.8 MHz?

[dempson@swell.actrix.gen.nz (David Empson)]

In article <m0ntXWq-00009QC@crash.cts.com> ncp@gnh-cathouse.cts.com (Neal Pitts) writes:
> Wait, let me understand this - DMA should be done at 1 MHz because of backward
> compatability with the IIe or because it's safer to let DMA happen at 1 MHz? 
> If it's for backward compatability, the Rev. D RamFAST only works on the GS
> anyway...

No, DMA should be done at 1 MHz because the slot bus runs at 1 MHz.
The clock frequency is fixed at 1 MHz, and all the bus signals required
for DMA are timed relative to that.  If the IIgs is running in fast
mode, the slot address and data bus are invalid.

The information in the hardware reference manual vaguely implies that
DMA works to fast areas of RAM while the IIgs is running at 2.8 MHz.
What it actually means is that you can do a 1 MHz DMA cycle to fast
RAM while the IIgs is running in fast mode, but you may cause the
processor to restart an instruction.

(To DMA into slow memory, the IIgs must already be running at 1 MHz).
-- 
David Empson                                                               
dempson@swell.actrix.gen.nz    <--- Note my new E-Mail address!            
Snail mail: P.O. Box 27-103, Wellington, New Zealand