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Re: Update on Carte Blanche status.



Michael J. Mahon wrote:
Alex, could you send me a sample configuration file?  It would be
very useful to give me an idea of the frequencies of the "ops" in
the file.


I've sent you a raw bit file. You can use free Xilinx tools to create other formats. The JTAG chain on the CB has just one chip - the S3250E FPGA.

-Alex.