Re: New ][ Hardware - DSP board (soon!)

[bazyar@teal.csn.org (Jawaid Bazyar)]

kpopple@imp.sim.es.com (Ken Poppleton) writes:

>In article <1993Feb25.210713.18808@mcs.anl.gov>, b45075@opal.ctd.anl.gov (Nathaniel Trost) writes:
>> Hmm, unless I'm mistaken it doesn't look like the board supports DMA transfers
>> to/from the GS memory.  Does the board support DMA?

>You are correct, I did not get a DMA controller on the board,  I would
>like to have one, but have not had the time to put that in.  This
>has mostly been a lack of understanging the requirements for a DMA
>controller which would operate on all the AppleII machines.  If you
>have a good reference to how DMA is done for a GS I would like to know 
>about it.  How much hardware does this take?  I am finding that the
>board is getting very full, and am unsure about the routing for the
>simple board I am now testing.  Can you recomend a low cost <$10 DMA
>controller chip?  Or how many pals and chips it would take!  Remember
>this must work for all AppleII's.

  DMA is quite easy to implement on the Apple II and IIGS.  Since it's
software controlled (i.e. the CPU must request a DMA action to occur since
there is no motherboard hardware arbitration of DMA requests) you just
signal the board to set up address/length and to begin the transfer.
The board then pulls RDY (I think - it may be another signal) and
starts blasting the address/data bus.  You need two 16-bit counters
and one 8-bit latch (for the bank address on a IIgs - that is, if
you want to DMA to "non-DMA compatible" RAMcards like the RAMFast D.)
One counter for the length of bytes remaining, one counter for the
address.  Perhaps one more for the address of RAM on the card.  That's 
all there is to it.  The Apple IIGS Hardware Reference tells all
there is to know in about a page (but it's more concise regarding
signals and timing and such).  On a pre-IIGS Apple II the operation
is much the same, if not exactly the same.
-- 
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