Re: Western design chip

[David.Empson@bbs.actrix.gen.nz]

In article <jpenne.728180702@ee.ualberta.ca> jpenne@ee.ualberta.ca (Jerry Penner) writes:
> cb408@cleveland.Freenet.Edu (Jason Reames) writes:
> 
> >I read in the Feb. issue of A+/InCider that Western Design has a chip for the
> >GS, the W65C81PL-E, that will double the speed of the GS.  Is this on the
> >level?  Anyone have one that can confirm it really works?  How about the
> >cost?  Thanks!!
> 
> Interesting concept, but I doubt it exists.

Yes it does.  It is just the so-called 14 MHz 65816, which can be used
with a ZIP GS or TransWarp GS.  Putting it into a standard IIgs will
make no difference whatsoever to its speed.

> It would have been neat if the 65816 "native" mode could have run
> instructions with new, better timings, while maintaining 6502 clock
> timings for emulation mode.

It does.  Most of the 6502 instructions that add an extra cycle when
crossing a page boundary are one cycle faster in native mode.  There
are still several 'internal operation' cycles, but it would need a
much more complicated processor design to be able to eliminate these.
At the very least, another internal data bus would be required.

> That way, MVP and MVN could have been done so each byte moved only
> took 2 clock cycles rather than 7.

No it couldn't.  At the very least, MVN/MVP would take 5 cycles per
byte: one to fetch the opcode, two to fetch the operands, one to read
the source byte and one to write the destination byte.  That doesn't
allow any spare cycles to increment the X and Y registers, decrement
the accumulator and test if it was zero, and adjust the program counter
back to the opcode again.

You may be wondering why the instruction needs to be re-fetched each
time.  The main reason is so that an IRQ can be handled after each
byte move.  If the processor did the move without refetching the
instruction, interrupts would be locked out for the whole move (up to
131072 clock cyles in the case of a 64k move, assuming 2 cycles per
byte moved).

I suppose it could watch for IRQ, and if it detected one, then
readjust the PC, etc. so that the instruction could be resumed.  This
would still need more complicated processor design, e.g. somewhere to
store the source bank number.
-- 
David Empson

Internet: David.Empson@bbs.actrix.gen.nz    EMPSON_D@kosmos.wcc.govt.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand