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Re: TWGS vs. ZipChip
- Subject: Re: TWGS vs. ZipChip
- From: toddpw@cco.caltech.edu (Todd P. Whitesel)
- Date: 4 Nov 1992 10:59:00 GMT
- Distribution: world
- Newsgroups: comp.sys.apple2
- Organization: California Institute of Technology, Pasadena
- References: <1cn33pINNiqd@gap.caltech.edu> <BwwE1A.3MF@well.sf.ca.us> <EewWhz600YUo1T=9wD@andrew.cmu.edu> <Bx00xx.MI4@xcluud.sccsi.com>
gtolar@xcluud.sccsi.com (Glynne Tolar) writes:
>I think I now know why. Zip is testing a new 4 layer board that will reduce
>noise on ROM 01 machines. If you buy a Zip >12 MHz I am told that is what
>you will get. They tell me the ROM 01s are just too noisey.
What a relief. It's good to hear that they are finally doing what the rest of
the industry has done for years -- go 4 layer and devote two to +5 and ground
planes. The two power planes act like a large capacitor, and really augment the
standard debouncing caps you're used to seeing next to every chip. (The ROM 03
is a two-layer design, but its layout is a masterpiece of noise isolation.)
Todd Whitesel
toddpw @ cco.caltech.edu