On Apr 3, 11:16 am, srk...@gmail.com wrote:
Maybe I should explain why this possible.
The FPGA on carte blanche is able to load its bit stream configuration
image from several sources. Carte blanche has two of these methods
implemented. The first is JTAG, with the highest priority, the second
is a generic SPI FLASH memory - an 8Mbit (1MB) FLASH device. If you
plug up a JTAG interface, the FPGA will always respond and accept data
over this interface, otherwise it will contact its dedicated SPI
interface and load a bit stream from there if its available.
Once the FPGA has booted, the dedicated SPI interface is relegated to
generic IO. This is where carte blanche can get its mits on the
interface and use the device for its own storage (the bit stream only
needs part of the device) which also allows us to reprogram the FLASH
with a new image if we wish to. On a power cycle, the FPGA once again
attempts to boot from SPI, and if a new image has been updated to
flash, it will load the new design into the FPGA.
OK. I guess the catch is then that the initial, and all subsequent
'personas' for the Carte Blanch will have to support the reprogramming
interface ?
That should work great, assuming nothing ever goes wrong ... :-)