Re: Microsoft Softcard and IIgs

[David Wilson <mcs6502@gmail.com>]

On Mar 13, 4:44 pm, mdj <mdj....@gmail.com> wrote:
> On Mar 13, 3:23 pm, David Wilson <mcs6...@gmail.com> wrote:
> > phi2 Low Pulse Width: Max 5000ns
>
> So the question is, does phi2 get held high?

Unfortunately, no.

The DMA' signal must be asserted during phase 1 of the 65(c)02 cycle
(when phase 0 (and phase 2) are low).
On a IIe with X5 and X4 left in the default state, phi0 = not(DMA or
PHI1) which is low when DMA is true.
If X5 and X4 are cut and soldered respectively, phi0 is no longer
gated by DMA'. You then need to ensure READY is deasserted to prevent
the 65(c)02 from executing instructions while DMA is active. See page
G-3 of Jim Sather's Understanding the Apple IIe.

The IIgs Hardware Reference (chapter 8) shows DMA being asserted
during the 1st half of the Apple II cycle and remaining asserted until
the start of the next cycle. It does not mention the possibility of
holding DMA asserted for more than one cycle.