Re: IIgs peculiarities

[dempson@actrix.gen.nz (David Empson)]

vladitx <vladitx@nucleusys.com> wrote:

> Just got interested in the IIgs and checked some documents about it.
> But the following questions remain unanswered (or I just missed
> something somewhere):
> 
> 1) IIgs ROM 03 has additional bit in the shadowing register (and the
> default 'enable') to include Text Page 2 ($800..$BFF), but the
> firmware keeps it disabled for some reason. And the "Alternate Display
> Mode" option is still available in the Control Panel.
> Where is the logic to this? Just leaving the register to shadow Text
> Page 2 is the way to go, and no "Alternate Display Mode" is needed at
> all.

Probably because of a reason like some third party software was
expecting to be able to use text page 2 in bank $E0, and having it
permanently shadowing from bank 0 would have corrupted whatever was
there.

At least the ROM 3 Alternate Display Mode control panel simply toggles
the shadow bit, rather than having to copy memory in an interrupt
handler.

> 2) I tried manually setting "Slow" speed by changing the high-bit of
> the appropriate register (through Monitor), but nothing happens. And
> the content of the register doesn't change. Is there IRQ subroutine
> keeping overwriting it? Or is there a special way to access it?

You can't do this directly, because the KEYIN routine saves and restores
the register containing the speed. You have to call a subroutine which
sets the bit.

> 3) IIgs maximum RAM - banks $00 .. $7F are specified as RAM range.
> This makes exactly 8MB. But the manuals keep saying 8.25MB. What is
> the truth and where those 256KB came from?

Anything saying 8.25 MB is simply wrong. The correct figure is 8.125 MB
(8 MB plus 128 KB).

The extra 128 KB is the "slow" memory in banks $E0 and $E1.

> 4) Memory expansion - according to what I've seen the connector
> provides for 2^10 rows/columns and 4 banks (CROW1/CROW0). This makes
> 4MB. How to go beyond this up-to 8MB? Is the signal "MSIZE"
> responsible and how?

Memory cards which support more than four "rows" do so via a mechanism
which has compatibility issues. They watch for the bank register value
output by the CPU on the data bus in the first half of a cycle, and
latch at least one bit. Some of them latch the whole thing and ignore
the CROW1/0 bits, while others synthesize a third row select bit from
one bit of the bank select register.

The compatibility issue is that DMA cycles don't output a bank in the
first half of the cycle, so a memory card which uses this technique is
not compatible with cards in I/O slots which use DMA.

There is one exception: the RamFAST SCSI card uses some trick to allow
DMA to work properly with these cards. I never heard the official story
of how they did this, but my speculation at the time was that the driver
does a normal CPU access to the target bank, which is sufficient to
latch the correct details into the memory card, then DMA cycles are
performed within that bank. It probably has to do with the CPU
repeatedly accessing the same bank to avoid bogus data appearing on the
data bus.

> 5) The memory expansion board may contain ROM, banks $F0+. Does the
> FPI know the installed ROM on the motherboard and redirect the other
> memory range to the expansion? Is pin #57 of FPI configuring this or
> FPI chips on ROM 03 are newer?

The area in banks $F0 through $F7 is reserved for a ROM disk, which is
supported by the built-in SmartPort firmware (in slot 5). Some memory
cards provided ROM or static RAM in this area (I had an OctoRAM ESP).
The firmware just looks for signature bytes at the start of bank $F0 to
see if there is a valid ROMdisk present.

Banks $F8 and higher (up to $FB on a ROM 3 IIgs, or $FD on ROM 00/01)
are reserved for expanding the firmware ROM. I believe they do map to
the ROM expansion area on the memory expansion card, but nothing is
allowed to use them. Some cards might have bent the rules and used this
area to enlarge the ROMDISK, and been bitten when the built-in ROM got
bigger with ROM 3.

To answer your specfic question: the FPI chips on the ROM 00/01 and ROM
3 are different. They even have different names: the ROM 3 on is "CYA"
(apparently short for "Control Your Apple").

The ROM 3 version has different memory mapping rules to deal with the
larger built-in ROM, the greater number of fast RAM banks on the
motherboard, and the fact that they have one more multiplexed address
bit. The CROW0 and CROW1 signals are generated based on a higher start
address than for the ROM 00/01.

> 6) If a ROM disk is to be present in banks $F0 .. $FB, what the format
> should be? Just a ProDOS image which then shows with it's volume name?

It has to start with the word ROMDISK, but I don't recall the other
details. I think there is a special driver starting immediately after
the signature bytes, which is used by the SmartPort firwmare. Apart from
the driver, the rest can be anything the driver wants, but it would
typically be a ProDOS block device.

In principle, a ROMDISK device could use bank switching within the card
to implement even more memory than 512KB, as long as it stays within
banks $F0 through $F7.

-- 
David Empson
dempson@actrix.gen.nz