Re: Stellation Mill 6809 card clone / FPGA

[MdntTrain <js@cimmeri.com>]

On Jan 13, 7:54 am, David Wilson <mcs6...@gmail.com> wrote:
> On Jan 13, 2:54 pm, MdntTrain <j...@cimmeri.com> wrote:
>
> > Alex, Given that CPUs are available (yes, Steve H), does it make sense
> > to implement this in an FPGA?   Seems really easy with just SSI
> > components... or maybe some PALs?
>
> I would probably design a Mill replacement using only DIL parts - CPU,
> ROM and CPLD (GAL) plus possibly a buffer or two. Should fit into a
> card no longer than the edge connector and not require such fine
> soldering skills as an FPGA design. If I were getting one
> professionally manufactured/assembled then that would change things.
>
> Lucky those Jameco parts are 6809E and not 6809 as the external clock
> version is needed by the mill design.

Would you or anyone else here be willing to walk me through board
creation and production, perhaps even for hire?   My skill level is
that I could easily build this board using point to point solder
wiring, but I've never done anything using computers -- design,
layout, gerber files, and such.   I believe I'd just need the basic
steps, and perhaps a check of my work at the end of each step.

If I end up making a run of these boards, if anyone wants them, or
making a website of the info, then of course co-credit will be given.
Anyone interested?

Thanks,
  JS