Ferdinan Meyer-hermann wrote:
To: Michael J. Mahon
Michael J. Mahon wrote:
Cool, Ferdinand!
I think this could work, provided that a special driver for PB1 was
added (according to IIc docs, you can't drive a IIc PB input with an
emitter follower). Of course, all the needed power is available at
the disk connector.
One could also use the WRITE PROTECT signal for reading from the net to
allow for a one-connector solution, as the signal can be easily driven by
a '125, which then can also replace the output circuitry above (with the
other three units of an AC125 wired in parallel, one would have 75mA
guaranteed drive capability).
3x74AC125 in parallel
|\
PH0-----| >---|>|-----+--------->NadaNet
|/o |
| |
/EN-----+-+ |
| |
o/| |
WPROT---< |-----------+
\|
74AC125
The signal can be read in the high bit of $C0EE, if the controller is
configured for checking write protection (STA $C0ED).
With some multiple of 0.5us latency in rise and fall times, no doubt...
I'd have to do some experiments with WRPROT to determine any limits
on timely sensing.
And the diode should just be an emitter follower to OR onto the net.
And the send routine always turns off the output, PH0 in this case.
There is one coding issue--today there is no common "exit" for
NadaNet, so disabling would require some rework. (This same
issue would have to be addressed to deal with IIgs speed control.)
I wouldn't think that there are so many exits that you can't just add
an STA $C0E8 to all of them (Although thats not a good style)
For the IIc, a single instruction in a few places wouldn't be a
deal-breaker, but for the IIgs, it's several instructions in a
few places. That makes it appropriate to consolidate the exits.