Re: Reporting Data 1-Way-Out?

["mdj" <mdj@1:124/5009.remove-xtk-this>]

  To: Michael J  Mahon
From: mdj@familynet-international.net

On May 30, 12:21 pm, "Michael J. Mahon" <mjma...@aol.com> wrote:

> > SmartPort devices treat PH0 as REQ, and WRPROT as ACK. To start a
> > communication, the host activates REQ(PH0), waits for ACK(WRPROT),
> > then sends a command packet 'writing' the data. REQ goes low at the
> > end of send, and when ACK goes low that signals the host to 'read'
> > back from the Smartport device.
>
> > If for example one wanted to make a //c nadanet adapter, one could
> > follow the above standard, and use PH2 to transmit, and WRPROT to
> > receive. If you only allow the device to be active during PH1+PH3,
> > you'll avoid any spurious data infesting the network during SmartPort
> > initialisation or disk activity.
>
> > It's also worth pointing out that /IRQ is available at the //c disk
> > port, which provides a whole other level of options.
>
> Frankly, that level of complexity would seem to suggest a
> small microcontroller rather than a couple of TTL parts...

If you're implementing a SmartPort device, yes. For the above mentioned 
purposes, all you need is PH1 + PH3 + /ENABLE2. That's 1 TTL part (a 7410) or a 
few signal transistors + resistors, depending on what you find easier to solder 
to the back of a disused DB-19 connector.

This works fine unless you want to have other devices hanging on the bus, it 
which case you need to gate /ENABLE2 on its way through. As simple as ORing 
PH1+PH3 with /ENABLE2 and the output goes down the chain...

> Put another way, a game port, it's not.  ;-)

Well, 2 outputs and an input isn't *quite* a game port, but it's close enough 
for many purposes :-)

Of course, there's another 2 inputs available on the mouse/joystick port, but 
one must recognise that unlike the other machines these are connected 
differentially to paired opto-isolators. If you want them to behave like a 
gate, you need wire them up via a PNP transistor, which will then invert the 
logic.

Matt
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