While my first try to connect a Disk ][ to the PC's parallel port has
proven to be unreliable, I'll try a second.
I chose to do the clock recovery and deserializing in hardware this
time. This is my idea:
http://sbscs.game-server.cc/appleii/disk2pc/disk2pc2.png
(I'm sorry, but I couldn't fit that into ascii art)
Principle of operation:
The values of R3,R4 and C3 are chosen that the 555 will output short
pulses at 250kHz.
These pulses clock the shift register. If a one is read the 555 will
be reset, causing the output to go low clocking the shift register to
input a "1". Because the first cycle after a reset is 37% longer and
the reset pulse will last a moment, the next clock pulse will be ~6 us
after the last read pulse which is perfect sync (if I am right...)
When the high bit reaches the last bit, the shift register is clocked
and the high bit toggled. Since it is always 1 it doesn't need to by
sent to the PC. Then the shift register is cleared to take up the next
byte.
R1/C1 provides some setup time for the '574 and R2/C2 for the hold
time.
In case of a self-sync byte, the shift register will be shifted 10
times before a 1 appears so the sync mechanism also works.
The PC only has to read the parallel port every 32 �s which is a very
relaxed requirement now.
Writing to disk could be done by bit-banging, since there is no need
to sync. And reproducing a precise timing is possible (at least in DOS
with interrupts turned off)
Am I right in my assumptions or is there any mistake?
Do you think this is workable?