On Nov 20, 11:42 pm, ferd...@gmx.de wrote:At the moment I'm thinking of a real analog PLL to recover the original clock and use it to clock a shift register.BTW, a system that just syncs to the data stream is NOT a PLL.
I know real analog PLLs were used once upon a time, but most floppy controllers used one of two kind of digital circuits.
FM/MFM controllers required a circuit to generate a "data valid" pulse that would be active at the time when a data pulse (if present) may arrive.
Simple systems used a counter that was reset by the incoming pulse. So center of the next valid period would always be 4 us away.
"Digital PLL" systems used a different approach. They adjusted the number of clocks to wait before the next valid data period depending on the previous pulses being early or late. This method provided better jitter tolerance. BTW the clock used was usually 8 MHz.
With the modern CPUs probably the easiest method of capturing floppy data is oversampling at say 4 MHz and doing the rest in software.
-Alex.