I study Logic Sequence ROM. It does not make sense when I look at Write
Sequence table. I decide to store $FF on data bus before data bus. Load
switch transfers $FF from data bus to data register. Shift switch continues
the state sequence to shift left one bit into QA like as MSB. QA is always
set for all 8 bits. The Write Signal toggles between two loops while QA is
set. It looks like this below.
QA Data Register Write Signal
0 11111111 0 Load $FF
1 11111110 1 Shift 1st bit
1 11111100 0 Shift 2nd bit
1 11111000 1 Shift 3rd bit
1 11110000 0 Shift 4th bit
1 11100000 1 Shift 5th bit
1 11000000 0 Shift 6th bit
1 10000000 1 Shift 7th bit
1 00000000 0 Shift 8th bit
QA is ideal to show digital bit stream. Write Signal is analog bit
stream. It controls the current in the coil of the read/write head. Also,
it has second head like as erase head.. The high/low state of the Write
Signal determines the direction of the magnetic field set up in the
read/write head. Please explain more about the field reversal and the lack
of field reversal why Write Signal is required to toggle while QA is always
set for all 8 digital bits.
I may be curious to see if I can simulate mangetic field to show field
reversal or lack of field reversal. It shows the same thing like Read
Pulse.
Bryan Parkoff