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Re: IIgs frozen in time!
- Subject: Re: IIgs frozen in time!
- From: David Wilson <mcs6502@gmail.com>
- Date: Thu, 27 Sep 2007 07:00:50 -0000
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On Sep 25, 8:14 am, Tristan Mumford <xtristan.xmumf...@xgmail.xcom>
wrote:
> True. If you feel the need to probe the clock with a CRO again could you
> please tell me if at all possible the relationship between the 1Hz line and
> the enable pin? Or actually the enable pin and data pin would be good to
> know. Basically I just want to know whether its active high or low.
1SEC is a square wave with no relation to CLK/DATA/EN* pins.
EN* is an active low enable (obvious from the name and the connection
marked -o| on the schematic). I was able to catch some low pulses as
the chip was read shortly after power up.
DATA idles low.
CLK idles high.
1SEC and DATA have pull up resistors.
If you need any further timing info I will need to hook up my logic
state analyzer.