Re: Transwarp II photos posted online

[heuser.marcus@freenet.de]

On Aug 26, 8:50 pm, R.Kiefer.S...@gmx.de (Ralf Kiefer) wrote:
>
> In 1988 (or 1987?)

Judging by the production date on the chips probably 1988.

> I bought an accelerator board constructed by a two-man-company
> in the south of West Germany (Leinfelden-Echterdingen).
> I actually do not remember the company's name :-(  They did this mainly
> to accelerate a chess computer. At this time these were mostly based on
> the 6502. But they used the Apple ][ bus and offered this card also to
> Apple users mainly running the processor with the NMOS instruction set
> @10MHz. There were some cards running @12.5MHz and mine was
> running the CMOS instruction set in a //e.

Sounds and looks terrific!

At the time I was still in school and a friend and classmate was heavy
into chess and CAC (computer aided chess) as he called it.

He once told me that there were rumors or announcements of a
6502-based chess computer clocked at an - at the time -
unbelievable 60 Mhz.
Sadly I don't know any more details but the clock rate literally
burned
into my brain ;-)

I didn't know of Apple II accelerators for chess but considering the
complete infrastructure (graphics, keyboard, "mass" storage and
development tools), the relative simplicity and better expandability
compared to other 6502-based machines they make sense.


> This card was build on two full length boards. Power consumption is
> 5A @5VDC. I had to upgrade the power supply and added a fan
> (real Pentium feeling ;-) ).
>
> The processor was based completely on PALs and standard TTLs.

The only way, I guess. When did WD bring their fast CMOS
versions to the market? In the 90ies?

Also I think it's quite small but then I'm not really a hardware guy.

> The whole main memory of an //e was held onto this card (144kB
> SRAM @50nsec, in 1988!).

Hmmm...why not the usual 128KB in a IIe? Any idea?

> There is no code caching.

What purpose had the Cypress RAM chips on the top card?
Separate zeropage and / or stack?

> The processor is forced to synchronous 1MHz by hardware only
> running the low level disk driver at slot 6. Screen memory is mirrored
> and written to mainboard memory in background but never read from
> slow mainboard memory. The whole set of soft switches is implemented
> "onboard" for reducing unnecessary access to mainboard RAM. I/O
> except slot 6 is implemented "a bit" asynchronous.
> If the last write access in background has not finished yet the fast
> processor idles (in hardware) while waiting. Read access to slot
> addresses is handled synchronous too.
>
> So my Apple //e was populated with the accelerator card at slot 7, disk
> controller (2* 640kB) at slot 6 and some RAM discs at slot 5 and 4 (up
> to 3MB). A nice little Apple //e :-)  Compiling & linking Pascal (UCSD)
> software was really amazing. The speed of mass storage (RAM disk,
> my own driver): reading 333kB/sec, writing 500kB/sec.

How many bytes did your driver program use? (weird question,
I know...)

> Assembling and linking the whole BIOS (SYSTEM.APPLE) was
> done in less than a minute :-)

A developers dream - that's for sure!

> Later I implemented a terminal emulation (not VT100, but similiar).
> I constructed a simple serial adapter based on a 6850, baud rate
> 57,6kBaud, 7N1 instead of 8N1 because of speed :-)  Every
> terminal command is finished before receiving the next character
> on the serial line, except scrolling the original Apple//e 80col.
>
> The price in 1988: AFAIR 1900 DM (950 Euros).

I guess that's a fair price for that kind of equipment - especially
considering the development effort and low sales numbers.

By the way: A great read, Ralf!

bye
Marcus