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Re: Read full 8-bit character from serial port (reprise)



On Jul 18, 2:41 pm, "david__schmidt"
<david__schm...@a2central.com.remove-7ow-this> wrote:
> Yeah, that should be fine.  Only variable left: the init routine.

Below is what I'm using for the init routine.  It is nearly identical
to yours, the only exception being that the baud rate is set by
another word which is run *after* this one.  That seems to be fine, as
sending characters works great.

It has to be something simple, I'm just not seeing it yet.

Ron

Init the modem port:

    org $800

;---------------------------------------------------------
; Zero page locations
;---------------------------------------------------------
PSPEED    = $6
BAUD      = $7
TEMPA     = $8
TEMPX     = $9

;---------------------------------------------------------
; Apple IIgs SCC Z8530 registers and constants
;---------------------------------------------------------

GSCMDB    = $C038        ; channel B (modem)
GSDATAB   = $C03A

GSCMDA    = $C039        ; channel A (printer)
GSDATAA   = $C03B

RESETA    = %11010001    ; constant to reset Channel A
RESETB    = %01010001    ; constant to reset Channel B
WR11A     = %11010000    ; init wr11 in Ch A
WR11BXTAL = %00000000    ; init wr11 in Ch B - use external clock
WR11BBRG  = %01010000    ; init wr11 in Ch B - use baud rate generator

;---------------------------------------------------------
; INITZSCC - initialize the Modem Port - baud rate must
;            be set after calling
; (Channel B is modem port, A is printer port)
;---------------------------------------------------------
INITZSCC:
    SEI
    LDA GSCMDB    ;hit rr0 once to sync up

    LDX #9        ;wr9
    LDA #RESETB   ;load constant to reset Ch B
                  ;for Ch A, use RESETCHA
    STX GSCMDB
    STA GSCMDB
    NOP           ;SCC needs 11 pclck to recover

    LDX #3    ;wr3
    LDA #%11000000    ;8 data bits, receiver disabled
    STX GSCMDB    ;could be 7 or 6 or 5 data bits
    STA GSCMDB    ;for 8 bits, bits 7,6 = 1,1

    LDX #5    ;wr5
    LDA #%01100010    ;DTR enabled 0=/HIGH, 8 data bits
    STX GSCMDB    ;no BRK, xmit disabled, no SDLC
    STA GSCMDB    ;RTS ;MUST; be disabled, no crc

    LDX #14    ;wr14
    LDA #%00000000    ;null cmd, no loopback
    STX GSCMDB    ;no echo, /DTR follows wr5
    STA GSCMDB    ;BRG source is XTAL or RTxC

    LDX #4    ;wr4
    LDA #%01000100    ;X16 clock mode,
    STX GSCMDB    ;1 stop bit, no parity
    STA GSCMDB    ;could be 1.5 or 2 stop bits
            ;1.5 set bits 3,2 to 1,0
            ;2   set bits 3,2 to 1,1

    LDX #11    ;wr11
    LDA #WR11BBRG    ;load constant to write
    STX GSCMDB
    STA GSCMDB

; Enables
    ORA #%00000001    ;enable baud rate gen
    LDX #14    ;wr14
    STX GSCMDB
    STA GSCMDB    ;write value

    LDA #%11000001    ;8 data bits, Rx enable
    LDX #3
    STX GSCMDB
    STA GSCMDB    ;write value

    LDA #%01101010    ;DTR enabled; Tx enable
    LDX #5
    STX GSCMDB
    STA GSCMDB    ;write value

; Enable Interrupts

    LDX #15    ;wr15

; The next line is commented out. This driver wants
; interrupts when GPi changes state, ie. the user
; on the BBS may have hung up. You can write a 0
; to this register if you don't need any external
; status interrupts. Then in the IRQIN routine you
; won't need handling for overruns; they won't be
; latched. See the Zilog Tech Ref. for details.

; LDA #%00100000 ;allow ext. int. on CTS/HSKi

    LDA #%00000000    ;allow ext. int. on DCD/GPi

    LDA #%00000000    ;allow ext. int. on DCD/GPi

    STX GSCMDB
    STA GSCMDB

    LDX #0
    LDA #%00010000    ;reset ext. stat. ints.
    STX GSCMDB
    STA GSCMDB    ;write it twice

    STX GSCMDB
    STA GSCMDB

    LDX #1    ;wr1
    LDA #%00000000    ;Wait Request disabled
    STX GSCMDB    ;allow IRQs on Rx all & ext. stat
    STA GSCMDB    ;No transmit interrupts (b1)

    LDA GSCMDB        ; READ TO RESET channelB POINTER TO 0
    LDA #$09
    STA GSCMDB        ; SET 'POINTER' TO wr9
    LDA #$00
    STA GSCMDB        ; Anti BluRry's syndrome medication

    CLI
    RTS        ;we're done!