On May 23, 7:21 pm, "Michael J. Mahon" <mjma...@aol.com> wrote:
Actually, it cannot safely cache "sub-bank-switched" regions of memory
without "knowing" their bank-switch protocols, and, unfortunately, the
$C800-$CFFE region is such a sub-bank-switched region. If it could be
made slot-specific, and the cache logic took the slot that originated
the /IOSTROBE into account, it could work, by disabling caching of the
extension space when switched in by certain slots. I don't know of any
accelerators that go to this length.
A lot of extra logic for a very small gain, I'd venture.
Indeed--but the question still hinges on how fast data can be moved
from RAM to sound RAM. I would actually expect a "slinky"-style of
interface to the sound RAM, considering what is stored there, but I
haven't yet taken the time to research it. (I figured someone who
knew this area well would chime in. ;-)
Yes. bandwidth to sound RAM might be impeded while the DOC is running,
necessitating faster Disk IO.
The DOC bandwidth shouldn't have to be very high, but who knows?
Certainly, the DOC has priority for access to the sound RAM.
I guess superficially speaking it *is* a 32 voice chip, and it seems
reasonable that whatever bandwidth it uses while active is constant,
regardless of the number of voices. I wish I had a IIgs hardware
reference handy.