Re: BYTE Article of Mega II

[David Wilson <mcs6502@gmail.com>]

On May 16, 6:18 am, "Michael J. Mahon" <mjma...@aol.com> wrote:
> A 3000-gate "gate count" is not particularly complex, even by the scale
> of 1984.
>
> "Gate count" usually refers to the number of 2-input NAND gates, and is
> often conventionally treated as one-third the number of transistors.

I found an IEEE paper that gives 3 NMOS transistors or 4 CMOS
transistors per gate.
http://ieeexplore.ieee.org/iel1/41/723/00019060.pdf?arnumber=19060

I also have a vague memory that the 6800 was so named because that was
about how many gates it contained. The IEEE paper lists it as ~4000
transistors.

> Since 64Kbit DRAMs were pretty commonplace in 1984, with transistor
> counts of 65000+, a gate count of 3000 seems like a pretty simple ASIC.

I think regular arrays like memory chips would pack more tightly than
random logic.