Re: 6502 trashing memory cycles...

["Bryan Parkoff" <nospam@nospam.com>]

<bieling@terra.es> wrote in message 
1173035529.995413.293070@n33g2000cwc.googlegroups.com">news:1173035529.995413.293070@n33g2000cwc.googlegroups.com...
> Hello,
>
> I've been having a look at the 6502 instruction details in the
> databooks and in uta2,p20..23. I've never realized that the 6502
> trashes so many memory cycles here and there. For example 3 out of the
> 6 cycles of an RTS are useless. 2 out of 4 of a PLA are useless, 1 out
> of 2 of a DEX are useless.
>
> The table in uta2,p22, shows the instructions classiffied in 29
> groups. 22 out of the 29 opcode groups trash between 1 and 3 memory
> cycles..!
>
> A clever circuit could make good use of so many memory cycles for some
> other purpose... any ideas ?

Jorge,

    Why do you think this way?  Let me give you the information below.  I 
don't think 3 out of the 6 cycles of an RTS are useless.


Cycle  Address Bus  Data Bus      External Operation  Internal Operation
1       0300           Opcode          Fetch Opcode           Finish 
Previous Operation, 0301 + PC

2       0301           Discarded Data  Fetch Discarded Data   Decode RTS

3       01FD           Discarded Data  Fetch Discarded Data   Increment 
Stack Pointer to 01FE

4       01FE           02              Fetch PCL              Increment 
Stack Pointer to 01FF

5       01FF           01              Fetch PCH

6       0102           Discarded Data  Put out PC             Increment PC 
by 1 to 0103

7       0103           Next Opcode     Fetch Next Opcode


    You can look at Synertek programming manual back to August 1976 from MOS 
Technology, Inc 1975.  It is useful for more information what you need to 
know.

Bryan Parkoff