Re: for the tinkerers / hackers (in the orig meaning of the word)

[bieling@terra.es]

a2fan@hotmail.com wrote:

> I mean, it reads fine - just slow it down when you need to set the time.

Michael J. Mahon wrote:

> Since ROM accesses are cached (except on "slow" slots), I don't
> see how an NSC can function, even for reading, while a cached
> accelerator is operating...

A2fan says "it reads fine", Mr. Mahon says "I don't see how".
I say I'm not sure, although I seem to recall that it didn't work on my
IIc+, (unless @ 1MHz).

It might be that the ROM in a IIc+ is never cached ?
That would explain that it reads fine even @ the faster IIc+ speeds ?
..or ?

Regards,
Jorge Chamorro.