bieling@terra.es wrote:
Michael J. Mahon ha escrito:a2fan@hotmail.com wrote:bieling@terra.es wrote:IIRC a No Slot clock won't work in a IIc+ unless it's running @ 1Mhz...Clock works fine ... you can only set it, at 1MHz.And the only reason for that is that the setting software uses timed loops to meet minimum delays, and they run too fast when accelerated and the clock can't keep up. The correct solution to this problem is to change the time delay routine(s) in the setting routine so that even at 30MHz the delay minimums are met. The clock is set so seldom that the additional milliseconds of delay at slow speeds is not a performance issue. -michaelI thought that ROM was cached... it isn't ?
Anything that deletes "real" accesses to the ROM addresses intercepted by the NSC would prevent the computer from being able to control it or to read it. If the NSC can be accessed for reading at high speed, then it should also be possible to set it as long as chip timing specs are met. Since ROM accesses are cached (except on "slow" slots), I don't see how an NSC can function, even for reading, while a cached accelerator is operating... -michael NadaNet networking for Apple II computers! Home page: http://members.aol.com/MJMahon/ "The wastebasket is our most important design tool--and it's seriously underused."