65C02 emulation

[Charlie Springer <RAM@regnirps.com>]

I am fiddling with emulation on the ARM again. Does anybody know performance 
of various emulators? Right now, in simulation I come very close to a 
one-to-one cycle count with an interpreter. In other words, an itty bitty 60 
MHz ARM chip should execute 65C02 instructions equivalent to a 40 to 50 MHz 
65C02.

Of course, this means a nice 520 MHz StrongARM should be like a 400 MHz 
65C02. On a card in an Apple slot, it has to slow down to original speed for 
various address ranges, but the rest of the time? In an Apple //e emulation, 
quite a number of calls, like 16 and 32 bit math, could be mapped to single 
instructions and some of the most common indexing schemes, ,x ,y etc, become 
single cycle on the ARM. The interpreter takes a cycle or two per 
instruction.

A recompiler or just-in-time translator could go even faster, but they don't 
interest me.

-- Charlie Springer