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Re: Hardware musings
mdj wrote:
Personally I'm not interested in doing the project unless I can come up
with a way to access the disk at the nibblized level to handle copy
protection,
I've put a bunch of thought into this myself.
Lets see, 4us per bit, .2s per track = 50k bits +3% means we would need
about 6.25k per track, or 25 256 byte pages. 256k would be the most one
would need to hold a 40 track file of A2 nibbles. Of course at the
front end you would want to place a table of all the tracks 0 through 40
including the quarter tracks. Each entry should have a track length (2
bytes) of formatted or 0 of not in use. You could build the disk
sequentially starting with track 0, followed by the data from the next
viable track, etc. The file would vary in length in 6.25k increments.
Standard disk image would be 36 track * 6.25k length + .25 header or
231k Plus or minus.
SST would need to be rewritten to save data in this format. Emulators
would probably also want to incorporate this new format. Maybe make a
new extension of apple2 nibble or a2n? How about .bst for bitstream?
The hardware would need several things:
- an asynchronous 4us timing circuit to 'rotate the disk' and point into
the track bit stream buffer for a read/write operation.
- A latch to push/ pull bits to/ from the bit stream.
- Have the bit read routing 'randomly' change the read more than 2
sequential 0s as 1s. (if easy)
- Have the write routine place the bits in the latch into the track bit
stream
- Have a timing circuit emulate the timing of a track seek and set the
bit stream to the proper place.
So the device would work something like this:
Timer advances at 4us rate (rotate disk bits)
On Read or write command: Add timer + Mod tracklength + track offset =
bits to start reading. Load bits into the latch as timer advances.
Clock them in until a read is requested or stop and 'latch' if you get
high bit to MSB, or just write the 8 bits into the stream at the proper
offset.
On Track change command, recalculate track offset, add seek delay to
timer for 'synchronizing' the bit stream.
Hardware should account for these asynchronous commands:
Motor on/ off
Stepper motor phase 0-4
Rotate bits into latch on read
Clear latch (even if a other operation is in progress)
Write latch into bitstream
Signals to send back:
Latch MSB is 1
Data in the latch