Re: Request a discrete refresh circuit schematic

["mdj" <mdj.mdj@gmail.com>]

PZ wrote:
> 72 pin simms would be more difficult since we only have an 8 bit data
> bus and 72 pin simms expect a minimum dbus of 16 bits.  I'm not saying
> you can't do it, there's a couple ways to implement 72 pin simms on an
> 8 bit bus, but it'll require some extra logic over the 30pin simms.

It really depends on whether you're talking single simms or not. Of
course, one 30 pin SIMM is relatively simple, but also rather small,
and once you're talking multiple 30 pin sockets, the complexity is
electrically comparable to a single 72 pin socket, but obviously much
more complex mechanically.

A good example is the 16mb 72pin SIMM, which is relatively simple to
work with, as it's essentially 4 sets of 4meg x 4 DRAM pairs with
independant CAS lines. With these, you can fairly simply decide which
of the 4mb 'banks' to activate as a part of the address decode (using a
simple 2-4 decode of a22 and a23) which will select the CAS line of the
appropriate bank plus a bus tranciever connected to that particular
banks 8 data lines. This isn't much different than implementing 4 30pin
SIMM sockets

The real complexity of 72 pin simms is the miriad of ways they can be
configured. For a hobbyist project, it's only really feasible to select
one particular simm type and support that. Personally I like the 16mb
modules as they're simple to decode non-wastfully, and since
essentially any size module can be bought for a song, I chose to work
with that one. A DRAM controller that can recognise and refresh most 72
pin SIMM types is a lot more electronics than is feasible in discrete
components.

If you're talking FPGA's or CPLDs, I borrowed and simplified a DRAM
controller from an open source music player design. I will dig out the
details if anyone is interested - their VHDL source is licensed under
the GPL

Matt