Re: RFC : SOME IDEAS FOR THE APPLE II FPGA'ers

[bieling@terra.es (Jorge Chamorro Bieling)]

Michael J. Mahon <mjmahon@aol.com> wrote:

> Exactly.  What is the objective?

?

> In fact, if you drop in a RISC core, you could implement the entire
> Apple II as a straightforward emulation on it, at very high speed.

A month or so ago I got the feeling that you were against using an ARM
for this purpose. But I may be mistaken.
Anyway, let's say that you can emulate the 6502 at a speed of 1 6502
instruction every X risc instructions (average). 

the job is (more or less):

1-fetch a 6502 opcode
2-use it to read from the jump table
3-jump accordingly
4-do whatever to emulate this opcode. This may include fetching some
operand(s), writing back to memory, etc.
5-Update P flags
6-jump to 1.

There is one memory cycle per 6502 opcode, one per byte for every 6502
operand, one additional cycle for every 6502 write, two more for
indirections, etc. 
Add to these the memory cycles to fetch the risc intructions themselves.

What speed do you get in AppleWin ?
Virtual II tops at 40MHz.

What do you think X could be ?
6502 speed = RISC core speed / X. (average)

Dou you think that this can ever run as fast as a hardware "emulation" ?

What is true is that this way you get an additional "layer" on top of
the Apple II. Much more flexibility. This is what I liked (remember that
thread ?) about this approach... but it won't run any faster, I think.