Jorge Chamorro Bieling wrote:
Michael J. Mahon <mjmahon@aol.com> wrote:Hard to fix in general, so the "slow mode" escape must always be provided....."Timing is everything."Furthermore,Sometimes, "timing" means much more than cycles per opcode Sometimes it is important even the *order* of the *events* that take place in the address/data bus *while* an instruction is executing. See for example the story about STA $C08F,X, in the chapter about the disk II, Understanding the Apple II, page 9-22. And the softwitch in the CFFA to deal with 6502 read-before-write cycles.And... who knows ? (but there are more of these, for sure)
Exactly. This is what I mean when I refer to the 6502 design, and the system designs based on it, being intimately coupled to memory and the memory bus behavior. This is a significant complicating factor for any "plug and play" Apple accelerator design. As far as I can determine, there has only been one "from scratch" cache-based accelerator design for the Apple, with all the others derived from it, either with ownership rights or without. -michael Music synthesis for 8-bit Apple II's! Home page: http://members.aol.com/MJMahon/ "The wastebasket is our most important design tool--and it is seriously underused."