Rev. C SCSI v2 from GSE-Reactive.com

["Henry" <apl2research(at)comcast.net>]

Hello everyone.

Just a quick update on the Rev. C SCSI CPLD project.  I know a few of you 
have been curious as to how this project is coming.

Here's a link to my Web Server with some pics:
http://reactivecomputers.gotdns.com/Rev.%20C%20SCSI/Rev.%20C%20SCSI%20v2/

The card is built.  The CPLD has been programmed.  I connect it to my 
external SCSI Hard Drive... and then notice the Hard Drive is dead.  What a 
disappointment!  It was working last week.  I had setup and formatted a 32 
Meg volume with a Rev. C SCSI card and was going to use it as a test volume 
for the Rev. C SCSI v2 prototype.  Oh well.  So much for plans.

Any one have a SCSI Hard Drive they would be wiling to sell me so I can 
replace the one in my external enclosure?  Doesn't need to be large, just 
working.

If you look at the pictures you'll notice the CPLD's pins are quite small. 
.5 pitch actually.  About three will fit in the width of the edge of a dime! 
Not fun soldering but I finally got the hang of it.  I don't hold much hope 
the prototype will work though.  Apple's design does work, but is really 
quite messy.  Signals 'feed' back in to places they shouldn't (to save PCB 
space and chips I guess) and coming up with code to emulate their design was 
really quite hard, if not impossible.  You may notice some small logic IC's 
still on the board.  The main reason for them is that they convert a 'week' 
1 or 0 (high or low) single to a true single.  You can't write a piece of 
code for a CPLD that says "if the voltage is 1.6 volts drop it to 0 volts or 
if it's 2.8 volts make it 5 volts".  Or I should say it can't be done in 
code and cheaper and in less parts then the original logic chip.  Since 
there won't be much demand for the Rev. C compared to the HS SCSI or RAMFast 
controllers completing a working model isn't a high priority.  We've learned 
a lot when it came to this project and that knowledge will be invaluable in 
future projects.  Next time a lot more time will be spent 'cleaning up' the 
actual design before any CPLD work would begin.  Not all issues can be over 
come by code.  We also learned that the Altera software is much easier then 
the Xilinx software and tends to lend itself to converting the older 
'through hole' designs better.  The next projects will probably use an 
Altera chip.

Just taking a break.  Back to my taxes. :-(


-- 
Henry S. Courbis
www.GSE-Reactive.com
Apple II Series Legacy Hardware - Come take a look at what we have to offer!