Re: How does the ZIP chip work?

["Bryan Parkoff" <none@nospam.net>]

"Michael J. Mahon" <mjmahon@aol.com> wrote in message 
news:-q6dnQri-J64w1jenZ2dnUVZ_t-dnZ2d@comcast.com...
> Jorge Chamorro Bieling wrote:
>> Eric <englere.geo@yahoo.com> wrote:
>>
>>
>>>I've been wondoring how the ZIP chip can speed up an Apple IIe. I
>>>understand it has a 4 Mhz 65C02 and it plugs into the original 6502
>>>socket.
>>>
>>>But, the original 6502 only has half of each 1 Mhz interval (I'm
>>>rounding to 1 Mhz to make it easier to discuss) to access memory
>>>because the video refresh circuit uses the other half. So, the orig
>>>6502 has a 500ns cycle to access memory.
>>>
>>>If the ZIP chip does not have it's own memory (does it?), then it can
>>>only speed up that part of the 1 Mhz cycle that is not used for video
>>>refresh. Assuming main memory could run 4X faster (which it can't),
>>>then it could bring that 500ns down to maybe 125ns. This means the
>>>overall processing (including the obligatory video cycles) would go
>>>from 1000ns to about 625ns, which is less that a 50% speedup.
>>>
>>>But main memory can't run any faster, so the zip chip must have some
>>>kind of cache? What am I missing here?
>>
>>
>> Yes, the zipchip has internal ram. It caches as much as it can. Once in
>> the cache, it does not need to access the mainboard ram for
>> reading/fetching/executing, only for writes and only if the write goes
>> to the screen buffers ot the i/o addresses (of course i/o addresses are
>> always read from the a2 mainboard). Also, there's a potential problem
>> with ram expansion cards (whose "pages" overlap the rom addresses) which
>> are activated using different addresses/schemes so you can tell the
>> zipchip to enable/disable caching for rom addresses($D000-FFFF). It
>> seems to me that the $c800-cfff range is also never cached as my videx
>> does not speed up much. The same goes individually for each slot's rom
>> addresses because some cards use the slot's rom address for i/o (the
>> videx screen buffer is a good example of this, starting at $cc00). To
>> deal with critical timing loops as is the case with diskII i/o, you can
>> configure it to switch to normal (1MHz) speed for "a while" when
>> accessing whichever slot (you usually set this only for slot 6). The
>> last zipchips ran at 8MHz internally..! and it looks like there were
>> even 10MHz rocketchips (I've never seen one).
>
> No, the Zip Chip is strictly write-through.  All writes slow down
> and go to Apple RAM (or whatever).  There is no "dirty" bit in the
> cache tag RAM.  To delay writes would complicate cache misses a
> great deal and would have to be defeated in any case for graphics
> and I/O addresses, as you note.
>
> Caching is defeated whenever "bank switching" can occur that is
> not tracked by the Zip Chip.  The I/O expansion ROM area ($C800..
> $CFFF) is an example of this.  It does, however, track the bank
> switching in RamWorks-type expansion cards up to 2MB.  This limit
> is dictated by the 8-bit x 8K tag ram:  3 bits for upper (64K)
> address bits, plus up to 5 bits for RAM card bank.  32 banks of
> 64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the
> main board.
>
> The Zip can be configured to slow down to 1MHz (run synchronously)
> for several kinds of references.  The slot I/O addresses are the
> most commonly stated, but the speaker address and the paddle trigger
> are a couple of others.  When a "slow mode" slot /DEVSEL address is
> referenced, the Zip resets an internal 53 millisecond timer.  It
> resumes accelerated execution when that timer times out.
>
> -michael
>
> Music synthesis for 8-bit Apple II's!
> Home page:  http://members.aol.com/MJMahon/
>
> "The wastebasket is our most important design
> tool--and it is seriously underused."

Michael,

    Is there a possibility that 6502 CPU chip and 65C02 CPU chip can run at 
14MHz without using accelerator?  Let say 14,318,180 crystal osc is on 
motherboard.  Video scanner depends on 14M crystal osc chip to run at 1MHz 
and RAM runs at 2MHz.  We may change the logic on the motherboard so CPU 
will run at 14MHz while "load/shift bit for video" is performed at the same 
time.  We can add switch like dip box to switch from 14MHz to original 1MHz. 
Cache and internal memory like Zip chip or Transwarp card may not be needed.
    Do you expect that it will work if we modify the logic on the 
motherboard to manipulate 14M crystal osc chip?

Bryan Parkoff