Re: How does the ZIP chip work?

[bieling@terra.es (Jorge Chamorro Bieling)]

Michael J. Mahon <mjmahon@aol.com> wrote:

> 
> No, the Zip Chip is strictly write-through.  All writes slow down
> and go to Apple RAM (or whatever).  There is no "dirty" bit in the
> cache tag RAM.  To delay writes would complicate cache misses a
> great deal and would have to be defeated in any case for graphics
> and I/O addresses, as you note.
> 
> Caching is defeated whenever "bank switching" can occur that is
> not tracked by the Zip Chip.  The I/O expansion ROM area ($C800..
> $CFFF) is an example of this.  It does, however, track the bank
> switching in RamWorks-type expansion cards up to 2MB.  This limit
> is dictated by the 8-bit x 8K tag ram:  3 bits for upper (64K)
> address bits, plus up to 5 bits for RAM card bank.  32 banks of
> 64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the
> main board.
> 
> The Zip can be configured to slow down to 1MHz (run synchronously)
> for several kinds of references.  The slot I/O addresses are the
> most commonly stated, but the speaker address and the paddle trigger
> are a couple of others.  When a "slow mode" slot /DEVSEL address is
> referenced, the Zip resets an internal 53 millisecond timer.  It
> resumes accelerated execution when that timer times out.

GREAT. This can be said louder, but not better.
-- 
Jorge Chamorro Bieling